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Freescale Semiconductor, Inc.
2,500
2,000
1,500
1,000
500
0
TYPICAL
WORST CASE
220
320
420
520 620 720 820
920
1020
.
C
IN
,
OR with the appropriate setup time
relative to the rising C
T
U edge of the clock. The assertion of the
D
ON
IC
M
SE
E any, If the match width is greater than 32 bits, the lower bits are
follows. The resulting effective rate of loading the CAM at L
SC
A
E
E
FR
BY
ED table initialized bits).
and entry queue. The flag register is set to 1C16 (setting the
HI
V
queue empty, buffered–entry mode, and
C
The error register is set to FFFF16, indicating no errors.
AR
Finally, the almost–full register is set to 3FFF16.
MATCH DUTY CYCLE AT 50 MHz INPUT CLOCK
Figure 3. Connections per Second vs Match Cycle Time
shortest–lived entries are placed near the end of the table. asserting the LH/SM signal
For an ATM application, this would correspond to the assign-
ment of small VPI values to permanent virtual circuits and MC output signifies the completion of the match cycle. If a
large VPI values to switched virtual circuits. match has been found, the MS output is also asserted. I f the
Note that at start–up, when entries are loaded into the match is a virtual path circuit match in ATM mode, the VPC
CAM via the fast–entry mode, the process is dominated by output will be asserted with the MS output. Output data, if
the time it takes to execute the initialization instruction that is enabled by the assertion of the G input.
start–up is approximately 240,000 entries per second. first latched into the MCM69C432 by the LL input. The match
cycle is then initiated as specified in the previous paragraph.
RESET
SIMULTANEOUS PORT OPERATIONS
Asserting RESET removes all entries from the CAM table
When the control and match ports are utilized simulta-
neously, certain procedures must be followed. If a CHECK
FOR VALUE command is issued, both the last operation
complete bit (bit 10) and the entry queue empty bit (bit 4) in
the flag register should be set prior to executing the CHECK
TIMING OVERVIEW
CONTROL PORT
The control port of the MCM69C432 is asynchronous.
Data transfers, both read and write, are initiated by the
assertion of the SEL signal. Address values should be valid
and WE should be high, when SEL is asserted to begin
a read cycle. All values (address, W E, an d SEL) should be
held until the MCM69C432 asserts DTACK to signal the end
of the read cycle.
Address and data values should be valid and WE should
be low, when SEL is asserted to begin a write cycle. Address,
data, WE, and SEL values should be held until the
MCM69C432 asserts DTACK to signal the end of the write
cycle.
MATCH PORT
The MCM69C432’s match port is synchronous in opera-
FOR VALUE command in order to receive valid results. How-
ever, matching on the match port can be done directly after
the last operation complete flag is set.
The match port has priority over the control port during
simultaneous operations.
DEPTH EXPANSION
Multiple CAMs can be cascaded to increase the depth of
the match table. The hardware requirements are very
straightforward, as the following pins on each device are sim-
ply wired in parallel: A2 – A0, DQ15 – DQ0, WE, IRQ ,
DTACK, MQ31 – MQ0, K, G, LH/SM, MC, MS, and VPC.
Four CAMs can be easily cascaded. Simulations show that
eight devices can be cascaded if care is taken to minimize
the length of the PC board traces connecting the CAMs.
The buffered –entry mode prevents multiple matching
entries in a single CAM. The check for value instruction
should be used to verify that multiple matching entries will
not result from a potential new entry. If a match is found in
tion. When the match width is
32 bits, a match cycle can be
CAM 1, for example, the new value should be placed in CAM 1,
initiated by presenting the match data on MQ31 – MQ0 and
where it will replace the existing entry.
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69C432 ? SCM69C432
11
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